New Details of Ivy Bridge Processors Revealed
New details of Intel Ivy Bridge processors have been revealed by Intel spokesperson at the International Solid-State Circuits Conference (ISSCC) in San Francisco recently. They revealed that the CPUs, manufactured on the 22nm fabrication process with 3D transistors, will support 20 PCIe Gen 3.0 interconnect lanes as well as an integrated DisplayPort controller.
Like Intel Sandy Bridge CPUs, the Ivy Bridge processors integrate memory controllers and GPUs which have been upgraded to support DDR3L DRAMs and Microsoft DirectX 11.0 graphics APIs. According to the spokespersons, Intel plans to introduce four variants of these processors and the first wave of their launch is targeted at computing devices that run the gamut from desktop, notebook, embedded, and single-socket server systems with up to 8 MB of cache.
One of the spokespersons, an Intel engineer named Mr. Scott Siers, said that Intel has spent considerable effort in making the CPU die modular so that different variations of the CPU can be created quickly. The largest die has four x86 cores and a large graphics block, which can be split along its x or y axis using automated tools to produce models with two cores or a smaller graphics block.
It remains to be seen if volume shipments of Ivy Bridge processors will be delayed and we shall have to wait for official confirmation on this matter.