CPU Guide

IDF Fall 2010 Day 1 - Sandy Bridge Revealed

IDF Fall 2010 Day 1 - Sandy Bridge Revealed

Another Leap Forward for Intel

If 0.68 seconds was nearly an eternity for an android (that was how long Data was tempted to join the Borg queen in Star Trek First Contact), then it's going to be a long grueling wait for the release of the next generation of Intel's latest processor codenamed Sandy Bridge - although it's just month's away. Slated for early 2011, the highly anticipated 2nd generation Intel Core processor family promises to deliver new and enhanced features that will further extend Intel's lead in the processor business. 

Fabricated on Intel's current 32nm process technology, Sandy Bridge is based on Intel's matured chip process which takes advantage of its high performance 2nd generation high-k metal gate transistors. When it comes to delivering the state-of-the-art logic silicon, no one comes close to beating them yet. So it's of no surprise when Intel also revealed that their next generation 22nm transistors are currently being fabricated in their fabs today and are making great strides in meeting its targeted release in late 2011.

Unlike the current generation Westmere processor, Sandy Bridge will be a highly integrated single die solution incorporating a graphics processor built into the same die as the main processor cores. Thus, one can expect better graphics processing capabilities since its memory controller and graphics are now interconnected using a new high speed, high bandwidth 'ring' architecture. The unique ring architecture allows the processor's cores to share its critical resources such as its cache with the graphics processor, thereby improving the overall performance of the computer while maintaining an energy efficient system.

The scalable ring architecture interconnect forms a link for all the critical components of the processor such as the cores, graphics, LLC (last level cache) and system agent. It provides 96GB/s of data bandwidth per connection and it is connected to a multi-bank cache, one bank for each core. For a four core processor, the ring interconnect can deliver a total of 384MB/s of low latency bandwidth to the cache while a dual core processor will deliver a total of 192MB/s.

Intel also created the ring interconnect to be modular in nature, such that it allows for the addition and removal of cores, graphics and cache with great ease. This would allow Intel to create multiple product SKUs based on various configurations for greater product variety and quicker deployment in the market. The removal of cache and cores can also be performed on the finished product, thereby allowing Intel to ship the same four core die, but with two of them disabled.