DDR3 - A Summary
DDR3 - A Summary
The major difference between DDR2 and DDR was the doubling of its bus speeds to the memory clock, thus allowing higher data transfer per memory clock cycle. DDR2 also increased its internal memory buffers from two to four bits. Official JEDEC data rates for DDR were 200-400Mbps and for DDR2, it was 400-800Mbps (DDR/DDR2 memory outside this range are all considered overclocked memory with no official specifications on its standards).
With DDR3, these parameters have been doubled yet again. Current JEDEC specifications for DDR3 set data rates between 800-1600Mbps and memory banks have increased to eight bits deep as well. As DRAM modules get larger, the deeper prefetch buffers will help reduce or mask the effects of latency. However, in order to sustain memory signal integrity at such high speeds, several new technologies have been integrated into DDR3 SDRAM modules such as a fly-by bus with On-DIMM termination. What the fly-by bus does is daisy chain address and control lines through a single path across each DRAM (and this has some similarities to how an FBDIMM module operates). In comparison, DDR2 memory splits the signal path between all DRAM chips through T-Branching.
Power consumption will go down with DDR3 memory, from the reference 1.8V of DDR2 to 1.5V with DDR3. At present, most DDR3 chipset are manufactured using 90nm technology, but there have been several vendors sampling 80-70nm chips as well. While this will unlikely further reduce the 1.5V standard that has been set, it will allow for better qualification of high-speed DDR3 memory in the future. Physically, DDR3 memory isn't all that different from DDR2, and DIMM modules come with the same 240-pin BGA package. However, they are not compatible with each other and will be notched differently so you cannot insert a DDR3 DIMM into a DDR2 slot and vice versa.
There is quite a bit more to DDR3, but these are the main features and improvements that would concern most users. As this article is about performance measurement and viability of DDR3 instead of a white paper dissection of the new technology, we won't bore you with details of every new feature and instead go straight to what is best understood - raw numbers.
|Voltage||2.5V +/- 0.2V||1.8V +/- 0.1V||1.5V +/- 0.075V|
|Source Sync.||Bi-Directional DQS (Single ended Default)||Bi-Directional DQS (Single/Differential Option)||Bi-Directional DQS (Differential Default)|
|Burst Length||2, 4, 8 (2-bit prefetch)||4, 8 (4-bit prefetch)||4, 8 (8-bit prefetch)|
|On-Die Termination (ODT)||No||Yes||Yes, Dynamic|
|Auto Self-Refresh (ASR)||No||No||Yes|
|Driver Calibration||No||Off-Chip driver calibratrion||Self Calibration with ZQ Pin|