Feature Articles

Intel's Silverthorne, Tukwila Updates and More

Intel's Silverthorne, Tukwila Updates and More

Tukwila, Memory and Integrated 'Radio' Design Updates

Tukwila - the 2-Billion Transistor Itanium Processor

On the other end of the processor technology scale, Intel unveiled its 2-billion transistor Itanium processor. Codename Tukwila and manufactured on a 65nm process technology, this behemoth of a chip easily doubles the performance of current Itanium processors as it is the first quad-core Itanium ever with only a 25% increase in power consumption (130W SKU). Tukwila also boasts other firsts for Intel as it features their QuickPath chip-to-chip direct interconnect technology (reminiscent of HyperTransport), dual integrated FB-DIMM memory controllers and 30MB of on-die cache. With Hyper-threading support, Tukwila processors can process up to eight threads simultaneously and is expected to have clock speeds up to 2GHz for the scheduled launch in the second half of the year. Not much else was shared, but we expect more to be revealed in Intel's Spring IDF this year as technologies such as QuickPath is expected to see light in other product segments late this year.

Memory Technology Highlights

Over on the memory technology front, Intel's joint venture with ST Microelectronics announced a breakthrough in Phase Change Memory (PCM) as well as demonstrate the world's first multi-level cell (MLC) device using PCM technology. As quoted from Intel, "It is a promising new memory technology that provides for very fast read and writes at lower power than conventional flash and allows for more stable data retention - possessing many of the best attributes of leading memory technologies. The move from single bit per cell to MLC also brings significantly higher density at lower cost per Mbyte - making the combined MLC on PCM a powerful development." The significance of all this is that in future, this can supersede NAND flash memory once it has evolved and matured enough. Given a long enough term to progress, it has the potential to even replace DRAM memory. As mentioned, this technology is fast and is non-volatile, making it the perfect balance in the world of memory. Note that NAND flash memory reads/writes in block-level whereas Phase Change memory manipulates data at the bit-level.

Moving to developments somewhat closer to our current timeline, Intel published a paper on a new category of integrated memory that can replace on-chip SRAM memory often used in processor caches at the moment. Intel demonstrated how a 2GHz 2Mb 2T Gain-Cell Memory built on native 65nm CMOS technology is able to deliver bandwidth as much as 128GB/s! SRAM is very fast, but costly in terms of die area required. DRAM on the other hand is far denser, much slower and can't be integrated on the processor due to process differences. This new Gain-Cell Memory on this demonstrated process however, is as fast as SRAM but with twice its memory density (and is faster than embedded DRAM or any other DRAM technology). While Intel doesn't expect to see this come to desktop processors anytime soon, they did reveal that this new memory cell technology would make its way into Intel's Tera-scale computing project where this level of density and speedy transactions are ideal to integrate them within the multitude of processing cores.

Wireless 'Radio' Revolution

In other developments, Intel published a paper on an integrated radio chip design implemented in a standard 90nm CMOS process that integrates dual low noise amplifiers (LNA) and high efficiency class-AB power amplifiers (PA) to support 802.11agn WLAN protocols. This single compact radio chip design is versatile and power efficient as opposed to existing discrete radios required to support both 802.11ag and 802.11n protocol needs. This integrated radio chip design will greatly facilitate the new wave of MID devices and slimmer, more power optimized handhelds, PDAs and other wireless products. Looking forward into the future, Intel has their sights set to deliver digital multi-radios which can support multiple protocols/standards via reconfigurable CMOS radios and tunable antennas.