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Intel Centrino Duo 'Napa' Mobile Technology Explained

Intel Centrino Duo 'Napa' Mobile Technology Explained



Intel Smart Cache

Intel Smart Cache

Critical numbers aside, one of the most impressive aspects of the Core Duo processor has got to be the Intel Smart Cache. Because of the design limitations where a single bus sits between the 2MB L2 cache and the two execution cores, concurrent access of the L2 cache by the two cores would be impossible. Although the two cores are able to have full access to the L2 cache, access is restricted to just one core at any given time. Compared to the access time and bandwidth if both cores were able to access the 2MB L2 cache simultaneously in a hypothetical two cores, independent bus design, you can clearly see that the access time available for L2 access in each core is halved for the Core Duo processor. This then is where the "Smart" bit of the Intel Smart Cache steps in.

To prevent the limited access time from severely impacting the overall performance due to the two core, one bus design, the Intel Smart Cache features a Bandwidth Adaptation Buffer that basically functions to ensure the bandwidth that is available to the L2 cache per core in Yonah stays virtually identical to that of its predecessors (Dothan and Banias) without incurring additional clock cycles, in essence virtually doubling average L2 bandwidth when both cores are active. On a sidenote, this also explains why the faster 667MHz FSB in return for higher bandwidth is necessary.

Another "smart" attribute lies in its dynamic cache allocation capability, which as its name implies means the L2 cache is constantly and dynamically adjusted to match the data load of each core. In doing so would allow the utilization of the L2 cache to be maximized. Also contributing to increasing the cache performance are optimized pre-fetchers and a deeper write output buffer.


Enhanced Intel Deeper Sleep

Where power is concerned, one of the biggest challenges thrown to the chip designers over at Intel was to ensure that the thermal design power (TDP) of the dual-core Yonah is better if not at least match that of the older 'Dothan' processor. While it is not difficult to raise computing performance, keeping power consumption under check while having more transistors and a faster bus speed is a tall order, even for Intel. On that note, if the latest Centrino Core Duo mobile technology is unable to provide the same kind of battery mileage consumers have come to expect from Centrino platforms, Intel will be looking at a sizeable lost in consumer faith. Furthermore, Centrino notebooks are not cheap, and all the more so for the latest Centrino Core Duo versions. Therefore, power consumption must be kept at least on par with previous generations of Centrino notebooks, or else there is not much value to speak off in going with a Centrino Core Duo notebook now is there?

Happily, the talented engineers over at Intel were able to come up with a number of power saving enhancements to overcome the seemingly impossible power consumption challenge. Other than the use of low VCC cache design, low-power transistors, Intel's second generation strained silicon process that is claimed to reduce electrical leakages by 30% and the familiar enhanced Intel SpeedStep technology, the entire L2 cache was designed such that in situations of inactivity or when the demand for cache memory is low, data stored in the L2 cache is automatically transferred into system memory and flushed before it is powered down to further conserve power. In doing so, current is only needed by the system memory (which is perpetually drawing current anyway) to sustain data caching, thereby allowing the last remaining parts of the processor to be powered down without interrupting the data execution process whatsoever. This ingenious process is what Intel terms as 'enhanced deeper sleep' or Enhanced C4 state. Also helping the cause are the independent sleep states of the two cores, which are controlled by new MWAIT commands from the operating system, thereby increasing the power management flexibility of the processor.

To mark this revolutionary change as Intel puts it, a brand new modeling scheme was devised in conjunction with the change in corporate identity. This would make it easier for consumers to differentiate between the old and new processors across the different platforms of Centrino. After all, you cannot possibly expect a complete recall of older Centrino notebooks just to free up shelf space to make way for the new now can you? Another useful information you should have at your fingertips is that new notebooks built on the 'Napa' platform may come fitted with either an Intel Core Duo or Intel Core Solo processor for which they are denoted as Intel Centrino Duo and Intel Centrino respectively. Readers should also realize that older 'Sonoma' Centrino notebooks would continue to retail alongside the two new 'Napa' variants

New Modelling Scheme
Intel Centrino Mobile Technology Clock Speed Price (USD)
Intel Core Duo T2600 with 2MB L2 cache, Intel 945GM chipset and Intel PRO/Wireless 3945ABG 2.16GHz $706
Intel Core Duo T2600 with 2MB L2 cache, Intel 945PM chipset and Intel PRO/Wireless 3945ABG 2.16GHz $702
Intel Core Duo T2500 with 2MB L2 cache, Intel 945GM chipset and Intel PRO/Wireless 3945ABG 2.0GHz $492
Intel Core Duo T2500 with 2MB L2 cache, Intel 945PM chipset and Intel PRO/Wireless 3945ABG 2.0GHz $488
Intel Core Duo T2400 with 2MB L2 cache, Intel 945GM chipset and Intel PRO/Wireless 3945ABG 1.83GHz $363
Intel Core Duo T2400 with 2MB L2 cache, Intel 945PM chipset and Intel PRO/Wireless 3945ABG 1.83GHz $359
Intel Core Duo T2300 with 2MB L2 cache, Intel 945GM chipset and Intel PRO/Wireless 3945ABG 1.66GHz $310
Intel Core Duo T2300 with 2MB L2 cache, Intel 945PM chipset and Intel PRO/Wireless 3945ABG 1.66GHz $306
Intel Core Duo T1300 with 2MB L2 cache, Intel 945GM chipset and Intel PRO/Wireless 3945ABG 1.66GHz $278
Intel Core Duo T1300 with 2MB L2 cache, Intel 945PM chipset and Intel PRO/Wireless 3945ABG 1.66GHz $274