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Intel's Next Generation Mobility and Beyond
By Zachary Chan
Category : Notebooks/Laptops
Published by Vijay Anand on Friday, 21st October, 2005

Third Generation Centrino on the Horizon

Intel's Centrino mobile platform has been so successful, it is now ubiquitous in the mobile market. Two years ago, Intel was still very much aggressive in the 'Gigahertz' race and while the second generation Centrino platform (Sonoma) had more raw performance, it also brought about increased power usage and a higher thermal ceiling, which basically equated to lower battery life.

With this year's Fall IDF, Intel has officially ended the 'Gigahertz' race and is now evangelizing 'performance per watt', with solutions that heavily focus on power savings. This brings us to the third generation Centrino platform (codenamed Napa), one we think is seriously quite revolutionary (since we're actually getting something brand new this time around, we're quite excited about it). We've touched on Napa earlier during our Spring IDF coverage, but this time we dig deeper to see just what makes it tick.

Composition of the Napa platform.


Re-engineered from the ground up, Yonah will be Intel's first dual-core mobile CPU plus it will also be the first mobile CPU manufactured on a 65nm process (with a 35nm gate length). Yonah will feature 151 million transistors (as opposed to 140 million for Dothan) and receive an FSB bump from 533MHz to 667MHz. As a successor to Dothan, Yonah will include updated media and floating point capabilities through general improvements of the SSE decoder as well as the addition of the SSE3 instruction set. Yonah will also feature Intel Virtualization Technology, but EM64T (64-bit instruction set) will not be included. Intel's stance at the moment is that adding EM64T to Yonah would have overshot their power envelop target. Furthermore, Intel believes that 64-bit application support is not yet widely adopted and Intel will only include EM64T into notebooks when the market demands it. Well, it seems that Intel's crystal ball must have predicted that the market would be demanding it by 2H 2006, since Yonah's successor would have EM64T included.

Pentium-M Chipset Comparison Table
Processor Model Banias Dothan Yonah
Manufacturing Technology 130nm (0.13 micron) 90nm (0.09 micron) 65nm (0.065 micron)
No. of Transistors 77 million 140 million 151.6 million
Die Size 82 mm² 84 mm² 90.3 mm²
Front Side Bus 400MHz 400MHz/533MHz 667MHz (Power Optimized)
L1 Cache (data + instruction) 32KB + 32KB 32KB + 32KB 32KB + 32KB
L2 Cache 1MB full-speed 2MB full-speed 2MB shared (Intel Smart Cache)
Form Factor mPGA479 mPGA479 PGA478 or BGA479
Thermal Design Power 24W 21W ~21W
Core Technolologies SSE, SSE2, Enhanced SpeedStep SSE, SSE2, Enhanced SpeedStep SSE, SSE2, SSE3, Enhanced SpeedStep, Virtualization Technology, Enchanced Deeper Sleep,

Unlike the first generation dual-core processors from Intel, which were based on a monolithic design where two complete execution cores were basically glued to a single die (Pentium D 'Smithfield'), Yonah will not be a simple matter of shrinking and slapping together two Dothan cores. Intel knew from the beginning that this method would have been quite inefficient as power consumption and TDP would have skyrocketed (Sonoma has already received enough flak for this). Then there is also the problem of the separate L2 caches on each core, which is inefficient not only in terms of cache underutilization, but also increase system overhead when one core needs to retrieve data from the other core.

To resolve this problem, Yonah's design will still feature two Pentium-M cores (Dothan based), but will share one common 2MB L2 cache. A shared arbiter bus interface will also take care of cache access. The difference? Elimination of redundant logic, signaling optimizations, reduction of transistor power leakage and a smaller die size all contribute to a more efficient processor.

Brand new dual core design approach delivers more performance-per-watt.

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